发明名称 Communication channel calibration for drift conditions
摘要 A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
申请公布号 US9628257(B2) 申请公布日期 2017.04.18
申请号 US201514932192 申请日期 2015.11.04
申请人 Rambus Inc. 发明人 Ware Frederick A.;Perego Richard E.;Hampel Craig E.
分类号 H04L7/00;H04L7/10;H04L25/02;H04L25/12;G11C7/04;H04L7/033 主分类号 H04L7/00
代理机构 代理人
主权项 1. A component, comprising: a receiver to sample arriving read data, retrieved from addressable memory space of a memory device, the read data arriving at the component via a bidirectional link during a normal mode of operation, the sampling performed according to an operational value of a sampling instant defined relative to a reference clock; circuitry to suspend the normal mode of operation to update the operational value of the sampling instant in order to account for timing drift, the circuitry to cause the receiver to, in iterations, use at least two other values of the sampling instant to sample values of a predefined data pattern arriving at the component from the memory device via the bidirectional link; circuitry to, for each value of the at least two other values of the sampling instant, compare the sampled values of the predefined data pattern against expected data, to obtain pass/fail data; and circuitry to update the operational value of the sampling instant in response to the pass/fail data, to obtain an updated value; wherein the component is to sample the arriving read data, retrieved from the addressable memory space of the memory device, following resumption of the normal mode of operation according to the updated value.
地址 Sunnyvale CA US