System and method for memory command queue management and configurable memory status checking

摘要

Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.

主权项

1. An integrated circuit chip comprising:
a memory; command receipt circuitry configured to receive commands from a controller of a memory system; command queue circuitry configured to rearrange the commands in a list of the commands in response to suspending execution of one of the commands in order for the list to be indicative of a rearranged order of execution of the commands; and poll response circuitry configured to send part or all of the list of commands in response to receipt of a poll command from the controller.