发明名称 Memory device for performing error correction code operation and redundancy repair operation
摘要 Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
申请公布号 US9626244(B2) 申请公布日期 2017.04.18
申请号 US201414208795 申请日期 2014.03.13
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 Sohn Young-soo;Park Kwang-il;Park Chul-woo;Son Jong-pil;Youn Jae-youn;Chung Hoi-ju
分类号 G11C29/44;G11C29/42;G11C29/04;G11C29/00;G06F11/10 主分类号 G11C29/44
代理机构 Muir Patent Law, PLLC 代理人 Muir Patent Law, PLLC
主权项 1. A memory device, comprising: a first memory cell block including a plurality of sub-blocks, each including a plurality of normal memory cells; a second memory cell block separate from the first memory cell block and including a plurality of failure recovery memory cells; a fail address storing unit configured to store fail addresses, the fail addresses including a first fail address and a second fail address, the first fail address and the second fail address indicating a first type of fail cells and a second type of fail cells respectively; a control circuit; and an error correction circuit, wherein the control circuit is configured to: receive addresses received from outside the memory device;compare the received addresses to the fail addresses;perform error correction using the second memory cell block by storing parity bits for error correction in the second memory cell block if the received address matches with a first fail address; andperform redundancy operation using the second memory cell block by accessing redundancy cells of the second memory block corresponding to fail cells of the first memory cell block if the received address matches with a second fail address.
地址 Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do KR