| 主权项 |
1. A computer system for reducing operand store compare (OSC) penalties, the system comprising:
memory configured to store instructions and data; and a processor comprising an instruction fetch unit, a cracking unit, an instruction decode unit, an issue unit, and a unit of operation (UOP) comparison unit that includes a load/store identification unit, a classifying unit, and a comparison unit, the processor configured to execute the instructions to perform a method comprising: prior to sending an instruction received from the instruction fetch unit to the issue unit for issuance of the instruction to an execution unit: cracking and decoding, by the cracking unit and the instruction decode unit, the instruction into one or more UOPs, each UOP comprising instruction text (itext) and including address determination fields required to form an operand storage address, the address determination fields including at least one of a base address field, an index address field, and a displacement address field; identifying, by the load/store identification unit of the UOP comparison unit, a load UOP among the one or more UOPs; categorizing, by the classifying unit of the UOP comparison unit, the load UOP into one of a plurality of groups of load UOPs according to a location of the address determination fields within the load UOP; comparing, by the comparison unit of the UOP comparison unit, values of the address determination fields of the load UOP with values of address determination fields of one or more previously-decoded store UOPs to detect a dependency between the load UOP and the one or more previously-decoded store UOPs, wherein one or more least significant bits of the load UOP are masked during the comparing; and forcing, by the comparison unit of the UOP comparison unit the dependency between the load UOP and the one or more previously-decoded store UOPs, wherein the forcing the dependency causes the load UOP to be issued after the one or more previously-decoded store UOPs. |
