| 发明名称 |
Multiple port shared memory |
| 摘要 |
Some of the embodiments of the present disclosure provide a system comprising: a shared memory unit and an arbiter that is configured to generate a clock signal, receive information regarding bandwidths of each of a plurality of agents, and determine a clock frequency or a sequence for selecting single agents among the plurality of agents to allow the single agents to transfer data in parallel from/to the shared memory unit in a single clock cycle of the clock signal, wherein the sequence is based, at least in part, on the bandwidths for each of a plurality of agents. The arbiter is also configured to cycle through the determined sequence for selecting the single agents among the plurality of agents to allow the single agents to transfer data from/to the shared memory unit in the single clock cycles. |
| 申请公布号 |
US9627014(B2) |
申请公布日期 |
2017.04.18 |
| 申请号 |
US201414570886 |
申请日期 |
2014.12.15 |
| 申请人 |
Marvell World Trade Ltd. |
发明人 |
Deng Suzhi;Chiang John Ming Yung |
| 分类号 |
G06F13/10;G11C7/10;G06F13/16 |
主分类号 |
G06F13/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A system comprising:
a shared memory unit; and an arbiter configured to
generate a clock signal,receive information regarding bandwidths of each of a plurality of agents,determine a clock frequency or a sequence for selecting single agents among the plurality of agents to allow the single agents to transfer data in parallel from/to the shared memory unit in a single clock cycle of the clock signal, wherein the sequence is based, at least in part, on the bandwidths of each of the plurality of agents, andcycle through the determined sequence for selecting the single agents among the plurality of agents to allow the single agents to transfer data from/to the shared memory unit in the single clock cycle. |
| 地址 |
St. Michael BB |
