发明名称 Carrier generator, radio frequency interconnect including the carrier generator and method of using
摘要 A carrier generator includes a phase accumulator configured to receive a frequency command word (FCW) signal. The carrier generator includes an adder connected to the phase accumulator; and a loop filter configured to receive an output of the adder. The carrier generator includes a plurality of tuning arrangements, each tuning arrangement is configured to receive an output of the loop filter. Each tuning arrangement includes an electronic oscillator configured to receive the output of the loop filter. Each tuning arrangement includes a voltage controlled delay line (VCDL) configured to receive an output of the electronic oscillator, and to provide a tuning arrangement output. Each tuning arrangement includes a phase detector configured to receive a corresponding recovered clock signal and a feedback from a corresponding tuning arrangement output. Each tuning arrangement includes a counter configured to receive an output of the phase detector and to provide an output to the VCDL.
申请公布号 US9628261(B1) 申请公布日期 2017.04.18
申请号 US201514969286 申请日期 2015.12.15
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Kuo Feng Wei;Jou Chewn-Pu;Chen Huan-Neng;Cho Lan-Chou;Shen William Wu
分类号 H04L7/02;H04L7/033;H04L27/00;H04L7/027 主分类号 H04L7/02
代理机构 Hauptman Ham, LLP 代理人 Hauptman Ham, LLP
主权项 1. A carrier generator comprising: a phase accumulator configured to receive a frequency command word (FCW) signal; an adder connected to the phase accumulator; a loop filter configured to receive an output of the adder; and a plurality of tuning arrangements, wherein each tuning arrangement of the plurality of tuning arrangements is configured to receive an output of the loop filter, and each tuning arrangement of the plurality of tuning arrangements comprises: an electronic oscillator configured to receive the output of the loop filter;a voltage controlled delay line (VCDL) configured to receive an output of the electronic oscillator, and to provide a tuning arrangement output;a phase detector configured to receive a corresponding recovered clock signal and a feedback from a corresponding tuning arrangement output; anda counter configured to receive an output of the phase detector and to provide an output to the VCDL.
地址 TW