Low power flip-flop circuit

摘要

A 24-transistor D flip-flop circuit operates in a sampling mode when a clock signal has a first voltage state, and a holding mode when the clock signal has a second voltage state. The flip-flop circuit includes an internal control node coupled to a reference voltage node by way of a transistor controllable to couple the internal control node to the reference voltage node when the clock signal has the second voltage state. The flip-flop has very low power dissipation as it includes a 4-transistor change-sense component to detect changes in input data. The change-sense component is coupled in series with the transistor and receives an indication of an input voltage state of the flip-flop circuit and an indication of an output voltage state of the flip-flop circuit, and inhibits toggling of the internal control node if the indicated input voltage state and the indicated output voltage state are the same.

主权项

1. A flip-flop circuit that receives a clock signal and operates in a sampling mode when the clock signal comprises a first voltage state and in a holding mode when the clock signal comprises a second voltage state, the flip-flop circuit comprising:
a first transistor; an internal control node controllably coupled to a first reference voltage node by way of the first transistor, wherein the first transistor is controllable by the clock signal such that when the clock signal comprises the first voltage state the first transistor decouples the internal control node from the first reference voltage node, and when the clock signal comprises the second voltage state the first transistor couples the internal control node to the first reference voltage node; a change-sense component coupled in series with the first transistor, wherein the change-sense component receives at least one indication of a voltage state at an input of the flip-flop circuit and at least one indication of a voltage state at an output of the flip-flop circuit to inhibit the coupling of the internal control node to the first reference voltage node when the flip-flop circuit is operating in the holding mode if the indicated voltage state at the input of the flip-flop circuit and the indicated voltage state at the output of the flip-flop circuit are the same.