Field-effect transistor with dual vertical gates

摘要

A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.

主权项

1. A semiconductor device comprising:
a first vertical bar structure disposed over a substrate, wherein the first vertical bar structure includes a first sidewall and an opposing second sidewall; a first gate feature disposed along the first sidewall of the first vertical bar structure such that the first gate feature is electrically coupled to the first vertical bar structure; a second vertical bar structure disposed over the substrate, wherein the second vertical bar structure is electrically coupled to the first vertical bar structure and serves as a second gate feature; a first source/drain feature disposed in the substrate below the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure.