RAM at speed flexible timing and setup control

摘要

Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

主权项

1. A memory module comprising:
a module connected to a functional logic circuitry; a plurality of first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals, wherein the timing configuration circuitry provides a read and a write enable signal to a memory cell under test, and wherein the timing configuration circuitry is connected to a last scan-in chain latch, wherein a plurality of latches inside the timing configuration circuitry are loaded with predefined values; a plurality of selection circuits, wherein each output line of said plurality of said first timing control latches is connected to respective input lines of said selection circuits, and wherein output lines of said selection circuits are connected to a plurality of respective control input lines of memory cells under test; and wherein an output signal of said timing configuration circuitry is connected to input lines of said selection circuits, such that two sets of control data are operatively connected to said plurality of control input lines of said memory cells under test, without a reloading of said plurality of respective timing control latches, wherein a change between said two sets of control data operatively connected to said plurality of control input lines of said memory cells under test, is performed from a first clock cycle to a second clock cycle, wherein a first set of the input signals are applied for a write command and a second set of the input signals are applies for a subsequent read command, such that different sets of input signals are applied to the timing control input lines of said memory cells under test.