发明名称 Apparatus and method for power MOS transistor
摘要 A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.
申请公布号 US9627265(B2) 申请公布日期 2017.04.18
申请号 US201615075882 申请日期 2016.03.21
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Su Po-Chih;Chou Hsueh-Liang;Ng Chun-Wai;Liu Ruey-Hsin
分类号 H01L21/8234;H01L29/40;H01L29/423;H01L29/66;H01L29/78;H01L21/265;H01L21/28;H01L29/08 主分类号 H01L21/8234
代理机构 Slater Matsil, LLP 代理人 Slater Matsil, LLP
主权项 1. A method comprising: growing a first epitaxial layer over a substrate; growing a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer have different conductivity types; forming a first trench extending through the second epitaxial layer and partially through the first epitaxial layer; depositing a gate dielectric layer on sidewalls and a bottom of the first trench; depositing a gate electrode layer over the gate dielectric layer; applying a first etching process to the gate electrode layer, wherein as a result of performing the step of applying the first etching process to the gate electrode layer, a top surface of the first epitaxial layer is higher than a top surface of the gate electrode layer; forming a source region underneath a center portion of the bottom of the first trench; applying a second etching process to the gate dielectric layer until the source region is exposed; forming a second trench by removing a center portion of the source region, wherein the second trench extend through the source region and partially through the first epitaxial layer; forming a doped region having a first portion in the first epitaxial layer and a second portion in the substrate; and forming a field plate having a lower portion in the second trench and an upper portion in the first trench.
地址 Hsin-Chu TW