Arbiter verification

摘要

Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

主权项

1. A method of verifying operation of an arbiter in a hardware design, the arbiter receiving a plurality of requests over a plurality of clock cycles, the plurality of requests comprising a watched request, the method comprising, in a processor:
identifying, for each clock cycle, any requests received by the arbiter in that clock cycle; identifying, for each clock cycle, any requests output from the arbiter in that clock cycle; tracking a priority of the watched request relative to other pending requests in the arbiter using a counter, the counter updated based on the requests identified as being received by and output from the arbiter in each clock cycle and a mask identifying a relative priority of requests received by the arbiter in a same clock cycle; and verifying operation of the arbiter using an assertion written in an assertion-based language, the assertion establishing a relationship between the counter and a clock cycle in which the watched request is output from the arbiter.