发明名称 |
Dual power swing pipeline design with separation of combinational and sequential logics |
摘要 |
A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point. |
申请公布号 |
US9628077(B2) |
申请公布日期 |
2017.04.18 |
申请号 |
US201514638270 |
申请日期 |
2015.03.04 |
申请人 |
QUALCOMM Incorporated |
发明人 |
Xie Jing;Du Yang |
分类号 |
H03K19/00;H03K3/037;H03K19/0175;H01L25/065;G06F1/32 |
主分类号 |
H03K19/00 |
代理机构 |
Muncy, Geissler, Olds & Lowe, P.C. |
代理人 |
Muncy, Geissler, Olds & Lowe, P.C. |
主权项 |
1. A circuit comprising:
a first sequential logic element having a first sequential logic input, a first power supply input operable to receive a first power supply voltage, and a first sequential logic output; a combinational logic element having a combinational logic input coupled to the first sequential logic output of the first sequential logic element, a second power supply input operable to receive a second power supply voltage that is lower than the first power supply voltage, and a combinational logic output; and a second sequential logic element having a second sequential logic input coupled to the combinational logic output of the combinational logic element, a third power supply input operable to receive the first power supply voltage, and a second sequential logic output. |
地址 |
San Diego CA US |