发明名称 Page management approach to fully utilize hardware caches for tiled rendering
摘要 Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.
申请公布号 US9626735(B2) 申请公布日期 2017.04.18
申请号 US201314124845 申请日期 2013.06.24
申请人 Intel Corporation 发明人 Koker Altug;Navale Aditya
分类号 G06T1/60;G09G5/393;G06F12/0802;G09G5/36 主分类号 G06T1/60
代理机构 Jordan IP Law, LLC 代理人 Jordan IP Law, LLC
主权项 1. A system comprising: a battery to supply power to the system; a frame buffer to include one or more tiles associated with an image, each of the one or more tiles including a plurality of pages; a cache; a host processor; and at least one computer readable storage medium including a set of instructions which, if executed by the host processor, cause the system to: identify the one or more tiles associated with the image;order a linear stream of pages associated with the frame buffer into an entirety of each of the one or more tiles; andallocate the linear stream of pages to the cache, wherein each of the pages is an addressable page included in the one or more tiles.
地址 Santa Clara CA US