Universal asymmetry correction for packet timing protocols

摘要

The notion of a “PTP aware” path is one current proposed approach to reduce asymmetry effects. In a fully PTP aware path there is the notion of on-path support mechanisms such as boundary clocks and transparent clocks at every switching or routing node. However, on-path support methods only address time-transfer errors introduced inside network elements and any asymmetry in the transmission medium, such as, for example, the fiber strands for the two directions of transmission, cannot be compensated for by on-path support mechanisms. Furthermore, in a real operational network, which may traverse different operational domains administered by different entities, full on-path support is a difficult challenge. In certain managed network scenarios full on-path support can be contemplated. Nevertheless, the universal asymmetry compensation method described herein mitigates the asymmetry in a network path, without requiring on-path support mechanisms such as transparent clocks and boundary clocks.

主权项

1. A clock device, comprising:
a memory storing a table which includes asymmetry time error estimates for a plurality of network paths, wherein each of the asymmetry time error estimates is determined based on at least differences between time error estimates of the clock device made using global navigation satellite systems (GNSS) timing signals and using timing packets exchanged via a corresponding one of the network paths between the clock device and a master device aligned to the GNSS system; and a processor programmed to correct a clock in the clock device by performing steps comprising:
determining a network path signature based on at least received timing packets, the network path signature comprising at least one of a round-trip delay estimate or delay estimates obtained with and without on-path support, andif the table includes an entry associated with the determined network path signature:
correcting, based on an asymmetry time error estimate in the entry, a time delay estimated using at least the received timing packets; andcorrecting the clock based on the corrected time delay estimate and time contained in the received timing packets.