发明名称 Tri-layer CoWoS structure
摘要 A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
申请公布号 US9627365(B1) 申请公布日期 2017.04.18
申请号 US201615007714 申请日期 2016.01.27
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yu Chen-Hua;Hou Shang-Yun;Lee Yun-Han
分类号 H01L29/00;H01L25/10;H01L23/522 主分类号 H01L29/00
代理机构 Slater Matsil, LLP 代理人 Slater Matsil, LLP
主权项 1. A package comprising: a first Integrated Voltage Regulator (IVR) die, wherein the first IVR die comprises: metal pillars at a top surface of the first IVR die; a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars; a plurality of redistribution lines over the first encapsulating material and the first IVR die, wherein the plurality of redistribution lines is electrically coupled to the metal pillars; a first core chip overlapping and bonded to the plurality of redistribution lines; a second encapsulating material encapsulating the first core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other; and an interposer or a package substrate underlying and bonded to the first IVR die.
地址 Hsin-Chu TW