9T, 8T, and 7T bitcells for 1R1W and single port static random access memories (SRAM) with single-ended read and single-ended write

摘要

The present patent application describes 9T, 8T, and 7T versions of bitcells used with 1R1W memories. It also describes 9T, 8T, and 7T versions of bitcells used with single port SRAM memories. Different circuits are discussed to support different bitcells and architectures mentioned above. Our 1R1W and single port bitcells and architectures give significant advantages over the conventional bitcells and architectures.

主权项

1. A memory architecture comprising:
a plurality of transistors arranged to form a bit cell, said bit cell comprising a first transistor, a second transistor, a third transistor and a fourth transistor configured to store a bit of data; a fifth transistor having a gate coupled to a Data Bar (DB) signal, said fifth transistor having a drain coupled to a drain of said first transistor; a sixth transistor having a gate coupled to a Data (D) signal, a drain coupled to a drain of said third transistor and a source coupled to a source of said fifth transistor; a seventh transistor having a gate coupled to said drain of said sixth transistor, and a source coupled to a ground or VSSCOL signal; an eighth transistor having a gate coupled to a Word Line (WL) signal, a source coupled to a drain of said seventh transistor and a drain coupled to a Read Bit Line (RBL) signal; a ninth transistor having a gate coupled to the Word line (WL) signal, a source coupled to said ground and a drain coupled to said source of said fifth transistor.