Semiconductor device with sloped sidewall and related methods

摘要

A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.

主权项

1. A semiconductor device comprising:
a multi-layer interconnect board comprising in stacked relation a lower conductive layer, at least one dielectric layer, and an upper conductive layer; said at least one dielectric layer having a recess formed therein with a bottom and sloping sidewall extending upwardly from the bottom, the sloping sidewall having an oblique angle with respect to the bottom of the recess; said at least one dielectric layer comprising upper and lower dielectric layers bonded together, said upper dielectric layer being ring-shaped with an opening therein also defining the recess; said upper conductive layer comprising a plurality of upper conductive traces extending across the sloping sidewall; said lower conductive layer comprising a plurality of lower conductive traces; a plurality of vias extending between said lower and upper conductive layers; at least one integrated circuit (IC) carried by said multi-layer interconnect board in the recess; a plurality of bond wires coupling upper conductive traces to said at least one IC; and encapsulation material adjacent said at least one IC and adjacent portions of said multi-layer interconnect board.