Apparatuses and methods for current limitation in threshold switching memories

摘要

Apparatuses and methods are described herein for limiting current in threshold switching memories. In an example, an apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell.

主权项

1. An apparatus, comprising:
a plurality of first decoder circuits; a plurality of second decoder circuits; an array of memory cells, each memory cell of the array of memory cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, each pair of first decoder circuits coupled via a respective first access line, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits, each pair of second decoder circuits coupled via a respective second access line; and a control circuit coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, the control circuit configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the memory cell.