发明名称 |
Metallized junction FinFET structures |
摘要 |
FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal. |
申请公布号 |
US9627410(B2) |
申请公布日期 |
2017.04.18 |
申请号 |
US201514718500 |
申请日期 |
2015.05.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Doris Bruce B.;Kerber Pranita;Reznicek Alexander;Rubin Joshua M. |
分类号 |
H01L29/00;H01L27/12;H01L21/84;H01L29/45;H01L29/66;H01L21/285;H01L21/324;H01L29/16;H01L29/161;H01L21/02;H01L29/08;H01L29/06 |
主分类号 |
H01L29/00 |
代理机构 |
Otterstedt, Ellenbogen & Kammer, LLP |
代理人 |
Morris Daniel P.;Otterstedt, Ellenbogen & Kammer, LLP |
主权项 |
1. A FinFET structure comprising:
a semiconductor-on-insulator substrate including a bottom semiconductor layer and an electrically insulating layer adjoining the bottom semiconductor layer; a plurality of semiconductor fins mounted to the substrate, each of the fins having base portions adjoining the electrically insulating layer and sidewalls including (110) surfaces; a plurality of parallel gate structures operatively associated with the semiconductor fins, the gate structures including sidewalls and extending perpendicularly with respect to the semiconductor fins; a first set of dielectric sidewall spacers adjoining the sidewalls of the gate structures; a second set of dielectric sidewall spacers adjoining the first set of dielectric sidewall spacers and covering portions of the source/drain structures; a plurality of pairs of unmerged epitaxial source/drain structures including (111) planes, each pair of source/drain structures being operatively associated with one of the semiconductor fins; a plurality of parallel, fin-shaped cavities between and separating each pair of source/drain structures, the cavities extending to the electrically insulating layer of the semiconductor-on-insulator substrate, and a metal silicide layer formed on the (111) planes of the epitaxial source/drain structures and adjoining the source/drain structures and filling the plurality of cavities. |
地址 |
Armonk NY US |