发明名称 MULTI-DIE PACKAGE COMPRISING UNIT SPECIFIC ALIGNMENT AND UNIT SPECIFIC ROUTING
摘要 A method of making a semiconductor device can include forming an embedded die panel by encapsulating a first semiconductor die and a second semiconductor die with conductive interconnects in a single step. An actual position of the first semiconductor die and second semiconductor die can be measured within the embedded die panel. The first semiconductor die and the second semiconductor die can be interconnected by a build-up interconnect structure comprising a first unit specific alignment portion aligned with the first semiconductor die, a second unit specific alignment portion aligned with the second semiconductor die, unit specific routing connecting the first unit specific alignment portion and the second unit specific alignment portion, and a fixed portion aligned with outline of embedded die panel and coupled to the unit specific routing.
申请公布号 US2017103927(A1) 申请公布日期 2017.04.13
申请号 US201615290897 申请日期 2016.10.11
申请人 DECA Technologies Inc. 发明人 Bishop Craig
分类号 H01L21/66;H01L23/538;H01L25/00;H01L23/00;H01L25/065 主分类号 H01L21/66
代理机构 代理人
主权项 1. A method of making a semiconductor device, comprising: forming an embedded die panel by encapsulating at least four side surfaces and an active surface of a first semiconductor die, a second semiconductor die, and side surfaces of conductive interconnects coupled to the first semiconductor die and the second semiconductor die with encapsulant in a single step; measuring an actual position of the first semiconductor die and an actual position of the second semiconductor die within the embedded die panel to obtain a rotation measurement of the first semiconductor die, a XY shift of the first semiconductor die, a rotation measurement of the second semiconductor die, and a XY shift of the second semiconductor die; and interconnecting the conductive interconnects of the first semiconductor die and the second semiconductor die by forming a build-up interconnect structure over the embedded die panel, the build-up interconnect structure being formed by: forming a first unit specific alignment portion aligned with the first semiconductor die,forming a second unit specific alignment portion aligned with the second semiconductor die,forming unit specific routing connecting the first unit specific alignment portion and the second unit specific alignment portion, andforming a fixed portion aligned with outline of embedded die panel and coupled to the unit specific routing.
地址 Tempe AZ US