| 发明名称 |
SYSTEM AND METHOD FOR PREDICTING LATENCY OF A VARIABLE-LATENCY INSTRUCTION |
| 摘要 |
A system for predicting latency of at least one variable-latency instruction, wherein a microprocessor includes at least one pipeline, the at least one pipeline having an instruction stream. The microprocessor is configured to issue at least one dependent instruction, execute the at least one pipeline to serve at least one variable-latency instruction, generate a result of the at least one variable-latency instruction, and serve the at least one dependent instruction by using the result of the at least one variable-latency instruction. |
| 申请公布号 |
US2017102948(A1) |
申请公布日期 |
2017.04.13 |
| 申请号 |
US201514879213 |
申请日期 |
2015.10.09 |
| 申请人 |
SPREADTRUM HONG KONG LIMITED |
发明人 |
BRANSCOME Jeremy L. |
| 分类号 |
G06F9/30;G06N7/00 |
主分类号 |
G06F9/30 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A system for predicting latency of at least one variable-latency instruction, the system comprising:
a microprocessor including at least one pipeline, the at least one pipeline having an instruction stream, wherein the microprocessor is configured to:
issue at least one dependent instruction;execute the at least one pipeline to serve at least one variable-latency instruction;generate a result of the at least one variable-latency instruction; andserve the at least one dependent instruction by using the result of the at least one variable-latency instruction. |
| 地址 |
Shanghai CN |
