发明名称 APPARATUS AND METHOD FOR AUTOMATICALLY ALIGNING DATA SIGNALS AND STROBE SIGNALS ON A SOURCE SYNCRHONOUS BUS
摘要 An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.
申请公布号 US2017102733(A1) 申请公布日期 2017.04.13
申请号 US201615389538 申请日期 2016.12.23
申请人 VIA TECHNOLOGIES, INC. 发明人 CANAC VANESSA;LUNDBERG JAMES R.
分类号 G06F1/12;G06F13/42 主分类号 G06F1/12
代理机构 代理人
主权项 1. An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising: a replica radial distribution element, configured to receive a lag pulse signal, and configured to generate a replicated strobe signal, wherein said replica radial distribution network comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe; a Joint Test Action Group (JTAG) interface, configured to receive control information over a standard JTAG bus, wherein said control information indicates an amount to adjust a propagation time; and a bit lag control element, configured to measure said propagation time beginning with assertion of said first signal and ending with assertion of said second signal, and configured to generate a first value on a lag bus that indicates an adjusted propagation time, said bit lag control element comprising: delay lock control, configured to select one of a plurality of successively delayed versions of said first signal that coincides with said assertion said second signal, and configured to generate a second value on a lag select bus that indicates said propagation time, wherein said delay lock control selects said one of a plurality of successively delayed versions of said first signal by incrementing and decrementing bus states of select inputs on a mux, and wherein said plurality of successively delayed versions comprises inputs to said mux, and wherein said plurality of successively delayed versions comprises outputs of a first plurality of series-coupled matched inverter pairs; adjust logic, coupled to said JTAG interface and to said lag select bus, configured adjust said second value by said amount prescribed by said JTAG interface to yield a third value that is output to an adjusted lag bus; and a gray encoder, configured to gray encode said third value to generate said first value on said lag bus.
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