发明名称 Signal Reconstruction in Sequential Logic Circuitry
摘要 A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit is disclosed. At least one input signal is associated to the sequential logic circuitry block. The method comprises simulating a value of the at least one output signal depending on the at least one input signal and determining a transfer function for computing the value of the output signal directly after the simulation timestamp depending on the input signal and/or on the value of the output signal directly before the simulation timestamp. The method further comprises computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function, if a reconstruction condition is fulfilled.
申请公布号 US2017103152(A1) 申请公布日期 2017.04.13
申请号 US201514882414 申请日期 2015.10.13
申请人 Synopsys, Inc. 发明人 Biswas Parijat;Datta Shyam;Chakraborty Subhrajyoti;Chakravorty Minakshi
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method for reconstructing at least one output signal associated to a sequential logic circuitry block of a circuit, at least one input signal being associated to the circuitry block, the method comprising: simulating a value of the at least one output signal depending on the at least one input signal; determining a transfer function for computing the value of the at least one output signal directly after a simulation timestamp depending on at least one of the at least one input signal and on the value of the at least one output signal directly before the simulation timestamp; and computing the value of the at least one output signal directly after the simulation timestamp as a function value of the transfer function if a predefined reconstruction condition is fulfilled.
地址 Mountain View CA US