发明名称 Variable Length Execution Pipeline
摘要 In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes SIMD requests by staggering commencement of execution of the requests from a SIMD instruction. When executing one or more operations for a SIMD iterative approximation algorithm, and an operation for another SIMD iterative approximation algorithm is ready to begin execution, control logic causes intermediate results completed by the pipelined execution resource to pass through a wait state, before being used in a subsequent computation. This wait state presents two open scheduling cycles in which both parts of the next SIMD instruction can begin execution. Although the wait state increases latency to complete an in-progress algorithm, a total throughput of execution on the pipeline increases.
申请公布号 US2017102942(A1) 申请公布日期 2017.04.13
申请号 US201615385544 申请日期 2016.12.20
申请人 Imagination Technologies Limited 发明人 Veith Kristie;Rarick Leonard;Manoukian Manouk
分类号 G06F9/30;G06F15/80;G06F9/38 主分类号 G06F9/30
代理机构 代理人
主权项 1. A computation apparatus comprising instruction issue logic for issuing instructions on a pipelined processing unit having a dynamic pipeline depth, and control circuitry configured to produce a control signal that indicates whether an instruction category that defines two or more separable portions of computation, each requiring multiple pipeline iterations, is available for scheduling an instruction for execution by said pipelined processing unit, wherein the instruction issue logic is configured to: determine, during a first stage, one or more categories of instructions available to be selected for execution, wherein determining one or more categories of instructions comprises receiving said control signal from said control circuitry; select, during a second stage, one or more instructions that are ready for execution from the one or more categories of instructions determined to be available during the first stage; retrieve, during a third stage, operands of the one or more selected instructions that are ready for execution; and output said retrieved operands to said pipelined processing unit for processing.
地址 Kings Langley GB