发明名称 SOURCE SYNCHRONOUS DATA STROBE MISALIGNMENT COMPENSATION MECHANISM
摘要 An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time. The bit lag control element has delay lock control that is configured to select one of a plurality of successively delayed versions of the lag pulse signal that coincides with the assertion the replicated strobe signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the lag pulse signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions comprises inputs to the mux, and where the plurality of successively delayed versions comprises outputs a first plurality of series-coupled matched inverter pairs. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the time.
申请公布号 US2017103790(A1) 申请公布日期 2017.04.13
申请号 US201615389517 申请日期 2016.12.23
申请人 VIA TECHNOLOGIES, INC. 发明人 CANAC VANESSA;LUNDBERG JAMES R.
分类号 G11C8/18;G06F1/12 主分类号 G11C8/18
代理机构 代理人
主权项 1. An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising: a replica radial distribution element, configured to receive a lag pulse signal, and configured to generate a replicated strobe signal, wherein said replica radial distribution network comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe; a bit lag control element, configured to measure the time between assertion of said lag pulse signal and assertion of said replicated strobe signal, and configured to generate a first value on a lag bus that indicates said time, said bit lag control element comprising: delay lock control, configured to select one of a plurality of successively delayed versions of said lag pulse signal that coincides with said assertion said replicated strobe signal, and configured to generate a second value on a lag select bus that indicates said propagation time, wherein said delay lock control selects said one of a plurality of successively delayed versions of said lag pulse signal by incrementing and decrementing bus states of select inputs on a mux, and wherein said plurality of successively delayed versions comprises inputs to said mux, and wherein said plurality of successively delayed versions comprises outputs of a first plurality of series-coupled matched inverter pairs; and a synchronous lag receiver, coupled to said bit lag control element, configured to receive a first one of a plurality of radially distributed strobes and a data bit, and configured to delay registering of said data bit by said time.
地址 New Taipel City TW