PROCESSOR WITH ARCHITECTURAL NEURAL NETWORK EXECUTION UNIT

摘要

A processor has an instruction fetch unit that fetches ISA instructions from memory and execution units that perform operations on instruction operands to generate results according to the processor's ISA. A hardware neural network unit (NNU) execution unit performs computations associated with artificial neural networks (ANN). The NNU has an array of ALUs, a first memory that holds data words associated with ANN neuron outputs, and a second memory that holds weight words associated with connections between ANN neurons. Each ALU multiplies a portion of the data words by a portion of the weight words to generate products and accumulates the products in an accumulator as an accumulated value. Activation function units normalize the accumulated values to generate outputs associated with ANN neurons. The ISA includes at least one instruction that instructs the processor to write data words and the weight words to the respective first and second memories.

主权项

1. A processor having an instruction set architecture (ISA), the processor comprising:
an instruction fetch unit that controls fetches of instructions of the ISA from memory into the processor; a plurality of execution units that perform operations on operands of the instructions to generate results of the instructions according to the ISA; the plurality of execution units includes a hardware neural network unit (NNU) to perform computations associated with artificial neural networks (ANN), the NNU comprising:
an array of arithmetic logic units (ALU);a first memory, coupled to the ALU array, that holds data words associated with ANN neuron outputs;a second memory, coupled to the ALU array, that holds weight words associated with connections between ANN neurons;each ALU multiplies a portion of the data words by a portion of the weight words to generate products and accumulates the products in an accumulator as an accumulated value; anda plurality of activation function units that normalize the accumulated values to generate outputs associated with ANN neurons; and the ISA includes at least one instruction that instructs the processor to write data words and the weight words to the respective first and second memories of the NNU.