| 主权项 |
1. A computer system for two stage log normalization, the computer system comprising:
one or more computer processors; one or more computer readable storage devices; and program instructions stored on at least one of the one or more computer readable storage devices for execution by at least one of the one or more computer processors, the program instructions comprising: program instructions to execute an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds, wherein executing includes presetting each of the one or more cores with the one or more different seeds, wherein the one or more different seeds are at least one of: a pseudo random value or a binary value, and evaluating the one or more different seeds for each of the one or more cores concurrently; program instructions to determine a seed from the one or more different seeds that locates a fail-condition; responsive to determining a seed from the one or more different seeds that locates the fail condition, program instructions to determine an upper bound and a lower bound of the fail-condition, wherein determining includes executing the exerciser image with the seed on each of the one or more cores for a range of cycles, wherein each of the one or more cores is set to stop at a different cycle within the range of cycles, searching from an initial cycle at the beginning of a test execution run where the fail-condition does not exist to a subsequent cycle of a test execution run where the fail-condition exists, and determining whether the fail-condition has occurred within the range of cycles executed on each of the one or more cores; responsive to a determination that the fail-condition has occurred within the range of cycles executed by at least one of the one or more cores, program instructions to determine a lowest cycle count in the at least one of the one or more cores where the fail-condition is an upper bound; responsive to a determination that the fail-condition has not occurred within the range of cycles executed by at least one of the one or more cores, program instructions to reset each of the one or more cores with a higher stopping cycle; program instructions to determine an exact cycle where the fail-condition occurs, wherein determining includes performing a plurality of distributed searches for the fail-condition across each of the one or more cores, wherein performing the plurality of distributed searches includes distributing a number of cycles between the upper bound and the lower bound across each of the one or more cores; program instructions to construct a multi-cycle trace for the fail-condition, wherein constructing includes performing one test execution per-cycle, including the exact cycle where the fail condition occurred, and extracting data from one or more cycles preceding the exact cycle where the fail-condition occurred, data from the exact cycle where the fail-condition occurred, and data from one or more cycles subsequent to the exact cycle where the fail-condition occurred; and program instructions to aggregate test data collected from a plurality of test executions. |
