发明名称 3D INTEGRATED CIRCUIT PACKAGE WITH THROUGH-MOLD FIRST LEVEL INTERCONNECTS
摘要 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
申请公布号 US2017103970(A1) 申请公布日期 2017.04.13
申请号 US201615389278 申请日期 2016.12.22
申请人 Intel Corporation 发明人 Mallik Debendra;Sankman Robert L.
分类号 H01L25/065;H01L21/56;H01L21/82;H01L25/00 主分类号 H01L25/065
代理机构 代理人
主权项 1. (canceled)
地址 Santa Clara CA US