| 发明名称 |
On-Chip Test Pattern Generation |
| 摘要 |
A chip is provided that includes an integrated circuit including a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains. The chip further includes an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains. |
| 申请公布号 |
US2017102431(A1) |
申请公布日期 |
2017.04.13 |
| 申请号 |
US201615287331 |
申请日期 |
2016.10.06 |
| 申请人 |
Lantiq Beteiligungs-GmbH & Co., KG |
发明人 |
Kukreja Himanshu;Ahmad Shakil |
| 分类号 |
G01R31/3185 |
主分类号 |
G01R31/3185 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A chip, comprising:
an integrated circuit comprising a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains, and an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains. |
| 地址 |
Neubiberg DE |
