发明名称 Data storage device increasing sequence detector clock frequency when bottleneck condition is detected
摘要 A data storage device is disclosed comprising a non-volatile memory (NVM). During a read operation, a sequence of signal samples is generated representing codewords stored in the NVM. The signal samples are buffered to generate buffered signal samples. The buffered signal samples are processed at a first frequency to detect a data sequence, and a bottleneck condition is detected associated with processing the buffered signal samples at the first frequency. When the bottleneck condition is detected, the buffered signal samples are processed at a second frequency higher than the first frequency to detect the data sequence.
申请公布号 US9619379(B1) 申请公布日期 2017.04.11
申请号 US201313787743 申请日期 2013.03.06
申请人 WESTERN DIGITAL TECHNOLOGIES, INC. 发明人 Chan Tom Sai-Cheung;Zhu Wenli;Cho Jaedeog;Banh Thao Hieu
分类号 G06F12/02;H03M13/29;G06F13/16 主分类号 G06F12/02
代理机构 代理人
主权项 1. A data storage device comprising: a non-volatile memory (NVM); and control circuitry operable to: during a read operation, generate a sequence of signal samples representing codewords stored in the NVM;buffer the signal samples to generate buffered signal samples;process the buffered signal samples at a first frequency to detect a data sequence;detect a bottleneck condition associated with processing the buffered signal samples at the first frequency; andwhen the bottleneck condition is detected, process the buffered signal samples at a second frequency higher than the first frequency to detect the data sequence.
地址 Irvine CA US