Semiconductor device with a P-N junction for reduced charge leakage and method of manufacturing the same

摘要

Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a p-n junction in a conductive layer. The method may allow for the production of semiconductor memory devices of reduced size.

主权项

1. A gate structure comprising:
a substrate; a first dielectric layer disposed along the substrate; a first conductive layer disposed along the dielectric layer; a second dielectric layer, and a third dielectric layer, wherein the second dielectric layer and the third dielectric layer are disposed along a sidewall of the first conductive layer and the second dielectric layer is disposed along and over the third dielectric layer, and wherein the first conductive layer comprises p-type dopants and n-type dopants and wherein the p-type dopants form a p-type dopant area and the n-type dopants form an n-type dopant area.