| 摘要 |
A gate pad electrode and a source electrode are disposed, separately from one another, on the front surface of a super junction semiconductor substrate. A MOS gate structure formed of n source regions, p channel regions, p contact regions, a gate oxide film, and polysilicon gate electrodes is formed immediately below the source electrode. The p well regions are formed immediately below the gate pad electrode. The p channel regions are linked to the p well regions via extension portions. By making the width of the p well regions wider than the width of the p channel regions, it is possible to reduce a voltage drop caused by a reverse recovery current generated in a reverse recovery process of a body diode. Breakdown of a portion of a gate insulating film immediately below the center of the gate pad electrode and breakdown of the semiconductor device are thus prevented |
| 主权项 |
1. A semiconductor device, comprising:
a first first-conductivity-type semiconductor layer; pn parallel columns wherein first-conductivity-type columns and second-conductivity-type columns are alternately disposed on a first principal surface of the first first-conductivity-type semiconductor layer in a plan view layout of stripes extending in a direction horizontal to the first principal surface of the first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer disposed on surfaces of the pn parallel columns opposite to the first first-conductivity-type semiconductor layer side; second-conductivity-type channel regions disposed inside the second first-conductivity-type semiconductor layer in a plan view layout of stripes extending in the direction horizontal to the first principal surface of the first first-conductivity-type semiconductor layer, and passing through the second first-conductivity-type semiconductor layer in a depth direction and making contact with the second-conductivity-type columns; second-conductivity-type well regions disposed inside the second first-conductivity-type semiconductor layer in a plan view layout of stripes extending parallel to a first direction in which the second-conductivity-type channel regions extend in stripes, and passing through the second first-conductivity-type semiconductor layer in the depth direction and making contact with the second-conductivity-type columns, and one end portion in the first direction of each of which is linked to one end portion in the first direction of the second-conductivity-type channel region; first-conductivity-type source regions disposed inside each second-conductivity-type channel region; second-conductivity-type contact regions that each make contact with the first-conductivity-type source regions, and that are disposed in a plan view shape of straight lines extending in the first direction, one on the inner side of the first-conductivity-type source regions inside each second-conductivity-type channel region; second-conductivity-type high concentration regions disposed one inside each second-conductivity-type well region in a plan view shape of straight lines extending in the first direction, and one end portion in the first direction of each of which is linked to one end portion in the first direction of the second-conductivity-type contact region; first gate electrodes which are each disposed via a gate insulating film, over the second first-conductivity-type semiconductor layer, and on the surfaces of portions of the second-conductivity-type channel regions, each sandwiched between the first-conductivity-type source region and the second first-conductivity-type semiconductor layer; an interlayer insulating film disposed on the surfaces of the first gate electrodes; a source electrode disposed on the interlayer insulating film and connected to the second-conductivity-type channel regions and the first-conductivity-type source regions via contact holes provided in the interlayer insulating film; a gate pad electrode electrically connected to the first gate electrodes and disposed, separately from the source electrode, in a position on the interlayer insulating film opposite to the second-conductivity-type well regions and the second-conductivity-type high concentration regions with the interlayer insulating film sandwiched in between; a first-conductivity-type drain region disposed on a second principal surface of the first first-conductivity-type semiconductor layer; and a drain electrode connected to the first-conductivity-type drain region, wherein the second-conductivity-type well regions have a width in a second direction which is perpendicular to the first direction, that is wider than that of the second-conductivity-type channel regions in the second direction. |
