Computer processor providing exception handling with reduced state storage

摘要

A computer architecture allows for simplified exception handling by restarting the program after exceptions at the beginning of idempotent regions, the idempotent regions allowing re-execution without the need for restoring complex state information from checkpoints. Recovery from mis-speculation may be provided by a similar mechanism but using smaller idempotent regions reflecting a more frequent occurrence of mis-speculation. A compiler generating different idempotent regions for speculation and exception handling is also disclosed.

主权项

1. An electronic computer architecture executing instructions of a program to process data and comprising:
(a) at least one processing unit executing instructions (b) an idempotent region identifier circuit:
(i) identifying boundaries between instructions defining groups of instructions whose execution is idempotent;(ii) identifying live-in variables at the boundaries and storing those live-in variables based on this identification; and(iii) identifying fine and coarse boundaries based on the live-in variables at the boundaries, the coarse boundaries having relatively fewer live-in variables than the fine boundaries according to a threshold; and (c) an exception management circuit
(i) responding to an exception thrown during execution of a given instruction to restart execution of instructions by the processing unit at a preceding boundary of an idempotent region, the preceding boundary selected to be a coarse boundary or a :fine boundary depending on a type of the exception: and(ii) loading at least one of the stored live-in variables upon restarting of execution of the instructions by the processing unit at the preceding boundary.