Data processor with a load instruction that branches based on a control register value and a bit or bits read from memory

摘要

The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.

主权项

1. A data processor comprising:
a CPU (Central Processing Unit) for executing an instruction included in an instruction set, wherein the instruction set includes a load instruction for reading data from a device disposed in a memory space, wherein the memory space is managed by the CPU, data read according to the load instruction has a format wherein the format consists of a data-read-branching-occurrence bit region and a payload data region, the data-read-branching-occurrence bit region being for storing a data-read-branching-occurrence bit, and the CPU includes
a data-read-branching control register for indicating whether the data-read-branching-occurrence bit is valid or invalid,at least one data-read-branching address register for holding a data read branching address,a read-data-analyzing circuit having an input coupled to receive data of the data-read-branching-occurrence bit region, the read-data-analyzing circuit being configured to analyze a bit value set on the data-read-branching-occurrence bit region and a value set on the data-read-branching control register, and having an output to which a result of the analysis is supplied, the analysis not considering data of the payload data region, andan instruction fetch unit having an input coupled to the output of the read-data-analyzing circuit, and being configured to set an address value on a program counter and to fetch an instruction based on an output value of the program counter, wherein an address value stored in the at least one data-read-branching address register is set on the program counter when the result of the analysis output by the read-data-analyzing circuit indicates that the value set on the data-read-branching control register shows that the data-read-branching-occurrence bit is valid and the bit value set on the data-read-branching-occurrence bit region shows occurrence of data read branching.