发明名称 Scalable geometry processing within a checkerboard multi-GPU configuration
摘要 Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
申请公布号 US9619855(B2) 申请公布日期 2017.04.11
申请号 US201113976843 申请日期 2011.11.18
申请人 INTEL CORPORATION 发明人 Doyle Peter L.;Boles Jeffery S.;Hunter Jr. Arthur D.;Koker Altug;Navale Aditya
分类号 G06T15/00;G06T1/20;G06T15/10 主分类号 G06T15/00
代理机构 Lynch Law Patent Group, P.C. 代理人 Lynch Law Patent Group, P.C.
主权项 1. An apparatus, comprising: a plurality of processor cores to perform three-dimensional (3D) graphics processing, each processor core including local storage to buffer geometry setup results; shared storage communicatively coupled to the plurality of processor cores, the shared storage to buffer vertex processing results provided by each processor core; and a bus communicatively coupled to the local storage of each processor core, the bus to distribute at least some of the geometry setup results among the plurality of processor cores, wherein the local storage comprises a First In First Out (FIFO) buffer, wherein the FIFO buffer includes two sets of read pointers, wherein one set of read pointers is to reference objects spanning only target pixels of the processor core that includes the FIFO buffer, and wherein the other set of read pointers is to reference objects spanning target pixels of the processor core that includes the FIFO buffer and target pixels of at least one other processor core.
地址 Santa Clara CA US