| 主权项 |
1. A communication system comprising:
a monolithically integrated system on chip device configured for a multi-rate and selected format of data communication, the device comprising: a silicon substrate member; a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol, the data input/output interface being configured for a number of lanes numbered from four to one hundred and fifty; an input/output block provided on the substrate member and coupled to the data input/output interface, the input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block, the SerDes block being configured to convert a first data stream of X into a second data stream of Y, each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate; a signal processing block provided on the substrate member and coupled to the input/output block, the signal processing block configured to the input/output block using a bi-direction bus in an intermediary protocol; a driver module provided on the substrate member and coupled to the signal processing block, the driver module coupled to the signal processing blocking using a uni-directional multi-lane bus configured with N lanes; a mapping block configured to associate M lanes to a plurality of selected laser devices for a silicon photonics device, whereupon N is greater than M such that a difference between N and M represents a redundant lane or lanes; a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to the silicon photonics device, the driver interface comprising a slicer block and being configured to transmit output data in a multi-level pulse amplitude modulation (PAM) format; a receiver module comprising a TIA block provided on the substrate member and to be coupled to the silicon photonics device using the multi-level pulse amplitude modulation format, and coupled to the signal processing block to communicate information to the input output block for transmission through the data input/output interface; a communication block provided on the substrate member and operably coupled to the input/output block, the signal processing block, the driver block, and the receiver block; a communication interface coupled to the communication block; a control block provided on the substrate member and coupled to the communication block; and a redundancy block configured to add at least a redundancy bit as a function of one or more data bits associated with data for data error detection and correction, wherein the redundancy block is configured for at least data error detection/correction coding selected from at least one of a Checksum or Cyclic Redundancy Check (CRC); and a network coupled to the monolithically integrated system on the chip. |
