Embedded SONOS based memory cells

摘要

Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

主权项

1. A device, comprising:
a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel, the gate stack including a dielectric layer on the substrate and a charge-trapping layer on the dielectric layer and an oxide layer overlying the chargetrapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate; a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate, the MOS transistor comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate; and a strain inducing structure overlying the NVM transistor and a surface of the substrate in the first region of the substrate.