Programmable circuits for correcting scan-test circuitry defects in integrated circuit designs

摘要

In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (CUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.

主权项

1. An integrated circuit comprising:
circuitry under scan test (CUST); scan-test circuitry comprising:
a scan chain of interconnected scan-chain elements, wherein the scan chain supports scan testing of the CUST;scan-test control circuitry connected to control operations of the scan chain to perform the scan testing of the CUST; anda set of programmable circuitry configured to provide a signal based on configurable data stored in one or more configurable memory cells of the set of programmable circuitry to selectively:
enable operation of the scan chain in response to a first set of the configurable data to perform scan testing of the CUST without modification, andadjust operation of the scan chain in response to a second set of the configurable data to perform modified scan testing of the CUST to correct a defect in the scan test circuitry.