发明名称 Dynamic load balancing for video decoding using multiple processors
摘要 A method and computer readable medium storing a corresponding computer program for decoding a video bitstream based on processors using dynamic load balancing are disclosed. In one embodiment of the present invention, the method configures multiple processors to perform the multiple processing modules including a prediction module by mapping the multiple processing modules to the multiple processors. One or more buffer queues are used among said multiple processing modules and the mapping the prediction module to the multiple processors is based on the level of the buffer queue. The multiple processors may correspond to a multi-core Central Processing Unit (CPU) comprising of multiple CPUs or a multi-core Digital Signal Processor (DSP) comprising of multiple DSPs to practice the present invention.
申请公布号 US9621908(B2) 申请公布日期 2017.04.11
申请号 US201213602193 申请日期 2012.09.02
申请人 MEDIATEK INC. 发明人 Chen Ding-Yun;Ho Cheng-Tsai;Ju Chi-Cheng;Tsai Chung-Hung
分类号 H04N19/436;H04N19/61 主分类号 H04N19/436
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A method for video decoding using multiple processors with dynamic load balancing, the method comprising: determining multiple processing modules associated with decoding a video bitstream, wherein the multiple processing modules comprise distinct processing modules including a prediction module; configuring said multiple processors to perform the multiple processing modules by mapping the multiple processing modules to said multiple processors, wherein one or more buffer queues are used among said multiple processing modules; and wherein said multiple processors comprise a first processor configured to generate output data to said one or more buffer queues and a second processor configured to retrieve input data from said one or more buffer queues, wherein said mapping the multiple processing modules to said multiple processors is based on multiple load configurations, wherein switching among the multiple load configurations is based on the level of said one or more buffer queues.
地址 Hsin-chu TW