Semiconductor device having plural data input/output terminals configured for write test and read test operations

摘要

Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

主权项

1. A semiconductor device comprising:
a plurality of first terminals; a plurality of second terminals, the second terminals being configured to receive a plurality of first test data in serial in a first test operation and to receive a shift clock signal in a second test operation; a third terminal; a plurality of buffer circuits; a plurality of data input/output lines each coupled between an associated one of the first terminals and an associated one of the buffer circuits; and a plurality of test circuit units, wherein each test circuit unit is coupled to an associated one of the data input/output lines by being connected to the associated data input/output line at a location between the first terminal associated with the associated data input/output line and the buffer circuit associated with the associated data input/output line, the test circuit units being connected in series, wherein in the first test operation, the plurality of first test data are sequentially supplied to the test circuit units, and the test circuit units supply the plurality of first test data to the data input/output lines in parallel, and in the second test operation, a plurality of second test data supplied from the buffer circuits are supplied in parallel to the test circuit units, and the test circuit units serially output the plurality of second test data through the third terminal synchronously with the shift clock signal.