Electrostatic discharge (ESD) control circuit

摘要

One or more electrostatic discharge (ESD) control circuit are disclosed herein. In an embodiment, an ESD control circuit has first and second trigger transistors, first and second ESD transistors, and first and second feedback transistors. The ESD transistors provide ESD current paths for ESD current generated during an ESD event. The first and second trigger transistors are on during normal operation to maintain the ESD transistors in an off state. During an ESD event, the first and second transistors are turned off to enable the first and second ESD transistors to provide ESD current paths. The first and second feedback transistors turn on during an ESD event to reinforce the on state of the ESD transistors and to reinforce the off state of the trigger transistors. In this way, the ESD control circuit stably provides multiple ESD current paths to discharge ESD current.

主权项

1. An electrostatic discharge (ESD) control circuit, comprising:
a first trigger transistor comprising a first trigger gate, a first trigger source, and a first trigger drain; a second trigger transistor comprising a second trigger gate, a second trigger source, and a second trigger drain; a first electrostatic discharge (ESD) transistor comprising a first ESD gate, a first ESD source, and a first ESD drain; and a second ESD transistor comprising a second ESD gate, a second ESD source, and a second ESD drain, wherein:
the first trigger source and the first ESD drain are directly connected to a first supply voltage rail;the second trigger source and the first ESD source are directly connected to a second supply voltage rail;the first ESD gate is directly connected to the first trigger gate; andthe first trigger drain is directly connected to the second trigger gate and the second ESD gate.