发明名称 |
Semiconductor device |
摘要 |
Disclosed herein is an apparatus that includes a first internal-potential generation circuit that generates a first internal potential from a power supply potential and that outputs the first internal potential to a first node, and an internal-potential force circuit that includes a first switch element provided between the first node and a second external terminal. The internal-potential force circuit causes the first switch element to enter into an off-state when the test signal supplied to a third external terminal is activated and a potential level of a first external terminal is a first level, and causes the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is a second level different from the first level. |
申请公布号 |
US9618562(B2) |
申请公布日期 |
2017.04.11 |
申请号 |
US201414472226 |
申请日期 |
2014.08.28 |
申请人 |
Micron Technology, Inc. |
发明人 |
Furutani Kiyohiro |
分类号 |
G01R31/26;G11C29/00;G11C29/12;G11C5/14 |
主分类号 |
G01R31/26 |
代理机构 |
Dorsey & Whitney LLP |
代理人 |
Dorsey & Whitney LLP |
主权项 |
1. A semiconductor device comprising:
a first external terminal configured to be supplied with a power supply potential from outside the semiconductor device; a second external terminal configured to be supplied with a first internal potential from outside the semiconductor device; a third external terminal configured to be supplied with a test signal to be activated when the semiconductor device enters a test mode; a first internal-potential generation circuit configured to generate the first internal potential from the power supply potential and output the first internal potential to a first node; and an internal-potential force circuit that includes a first switch element coupled between the first node and the second external terminal, the internal-potential force circuit configured to cause the first switch element to enter into an off-state when the test signal supplied to the third external terminal is activated and a potential level of the first external terminal is at a first level, and cause the first switch element to enter into an on-state when the test signal supplied to the third external terminal is activated and the potential level of the first external terminal is at a second level different from the first level. |
地址 |
Boise ID US |