Gray code counter

摘要

One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PLL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

主权项

1. A gray code counter, comprising:
a set of cells configured to output a gray code signal, the set of cells comprising:
a first cell configured to output a first gray code signal portion of the gray code signal based upon a clock signal and a high signal; anda second cell configured to output a second gray code signal portion of the gray code signal based upon a next clock signal and an early first signal provided by a pre-ready cell, the second cell comprising:
a flip-flop; anda multiplexer, wherein:
an input of the flip-flop is coupled to an output of the multiplexer;a first output of the flip-flop is coupled to a first input of the multiplexer such that a first signal that is output from the first output of the flip-flop is fed into the first input of the multiplexer; anda second output of the flip-flop is coupled to a second input of the multiplexer such that a second signal that is output from the second output of the flip-flop is fed into the second input of the multiplexer; and the pre-ready cell configured to provide the early first signal to the second cell, the early first signal corresponding to the first gray code signal portion output from the first cell, the pre-ready cell configured to operate based upon an early clock signal.