Structures for split gate memory cell scaling with merged control gates

摘要

A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.

主权项

1. A memory device having a first memory cell and a second memory cell in and over a substrate, comprising:
a first active region in the substrate including a first portion and a second portion; a first doped region in the first active region, the first doped region between and abutting the first portion and the second portion of the first active region, and a top surface of the first active region is substantially coplanar with a top surface of the first doped region; a control gate over the first doped region and extending past the first doped region over the first portion of the first active region on a first side of the first doped region and extending past the first doped region over the second portion of the first active region on a second side of the first doped region, wherein the first side is opposite the second side; a charge storage layer between the control gate and the first active region, and extending past the first doped region over the first portion of the first active region on the first side of the first doped region and extending past the first doped region over the second portion of the first active region on the second side of the first doped region; a first select gate over the first active region on the first side of the first doped region and adjacent to the control gate, the first select gate spaced apart from the first doped region by the first portion of the first active region; and a second select gate over the first active region on the second side of the first doped region and adjacent to the control gate, the second select gate spaced apart from the first doped region by the second portion of the first active region.