Pulse mechanism for memory circuit interruption

摘要

In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

主权项

1. A non-volatile memory system comprising:
a plurality of memory circuits, each including one or more arrays of non-volatile memory cells; a controller circuit to control the transfer of data between the memory circuits and a host connected to the memory system and to manage the storage of data on the memory circuits; and a bus structure connecting the controller circuit with the memory circuits, the bus structure including a common first bus line whereby the memory circuits indicate to the controller circuit the ready/busy status of the memory circuits, wherein each of the memory circuits indicates the ready/busy status thereof by application of a pulse to the first bus line, the duration of which is distinct for each of the memory circuits.