| 摘要 |
The invention discloses a thin film transistor drive circuit and a drive method thereof and a liquid crystal display device. The thin film transistor drive circuit includes a plurality of scan lines, a scan signal output port configured to sequentially apply a scan signal to each of the scan lines, and a plurality of logic circuits. Each of the logic circuits is connected with one of the scan lines and a control signal line. The logic circuits are added to a drive circuit, and an input control signal corresponding to a truth table of the logic circuit is input for a preset duration by using a logic relationship of the logic circuit, so that an output control signal output to a scan line can be obtained to improve a scan signal on the scan line, to improve a delay distortion at the time of being turned off. |
| 主权项 |
1. A thin film transistor drive circuit, comprising:
a plurality of scan lines; a scan signal output port configured to sequentially apply a scan signal to each of the scan lines; and a plurality of logic circuits, each of the logic circuits being connected to one of the scan lines and a control signal line, for receiving an input control signal from the control signal line, applying an output control signal to the scan line; wherein, when an enabling signal is loaded on the scan line for a first preset duration, inverting the output control signal for a second preset duration, so that a voltage level of the scan signal loaded on the scan line is the voltage level of a disabling signal; wherein, in the second preset duration, when the scan signal is the disabling signal, the voltage level of the disabling signal remains unchanged independently from a voltage state of the output control signal, when the scan signal is the enabling signal, if the input control signal loaded on the logic circuit is inverted from the enabling signal, then the output control signal loaded on the scan line is non-inverted from the enabling signal, so that the voltage level of the scan signal loaded on the scan line is still the voltage level of the enabling signal; and if the input control signal loaded on the logic circuit is non-inverted from the enabling signal, then the output control signal loaded on the scan line is inverted from the enabling signal, so that the voltage level of the scan signal loaded on the scan line is the voltage level of the disabling signal, wherein the second preset duration is in a range between 100 ns and 900 ns, and, wherein the first preset duration is determined by the expression as,
t=T=(Δt−Δt1), wherein t is the first preset duration; T is a duration for which the enabling signal is loaded ideally; Δt is the second preset duration; and Δt1 is the rise delay of a voltage or the drop delay of a voltage. |
