发明名称 INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS
摘要 A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.
申请公布号 US2017098024(A1) 申请公布日期 2017.04.06
申请号 US201514873072 申请日期 2015.10.01
申请人 Xilinx, Inc. 发明人 Aggarwal Rajat;Wang Zhiyong;Lu Ruibing;Das Sabyasachi
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method, comprising: executing on a processor operations including: generating a first netlist for a circuit design stored in a memory coupled to the processor; determining a placement of the first netlist on a target integrated circuit (IC) to produce a first placed design; performing a set of optimizations on the first placed design; recording the set of optimizations in an optimization history file; performing one or more optimizations specified in the optimization history file on the first netlist to produce a second netlist that is different than the first netlist; determining placement of the second netlist on the target IC to produce a second placed design that is different than the first placed design; and routing nets of the second placed design to produce a placed and routed circuit design.
地址 San Jose CA US