POWER STATE COVERAGE METRIC AND METHOD FOR ESTIMATING THE SAME

摘要

In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.

主权项

1. A method performed by at least one processor for managing verification cases for a module in a chip design, the method comprising:
creating an electronic system level (ESL) model comprising a plurality of blocks for the module; defining at least one ESL power state for each block of the plurality of blocks; selecting at least one verification case for each ESL power state of said at least one ESL power state; setting a target coverage value for each verification case of said at least one verification case; performing a register transfer level (RTL) simulation for said each verification case; receiving an actual coverage value for said each verification case; and updating the ESL power states and the verification cases for each block of said plurality of blocks.