Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect

摘要

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

主权项

1. A semiconductor device, comprising:
a first gate conductive structure defined in a gate level of the semiconductor device, the first gate conductive structure having a linear-shape and a lengthwise centerline oriented in a first direction parallel to a substrate of the semiconductor device; a second gate conductive structure defined in the gate level of the semiconductor device, the second gate conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the second gate conductive structure separated from the lengthwise centerline of the first gate conductive structure by a first distance as measured in a second direction, the second direction oriented perpendicular to the first direction and parallel to the substrate of the semiconductor device; a first diffusion region positioned along a portion of a first side of the first gate conductive structure; a second diffusion region positioned along a portion of a second side of the first gate conductive structure, the second diffusion region also positioned along a portion of a first side of the second gate conductive structure, wherein the first gate conductive structure and the first diffusion region and the second diffusion region together form a first transistor; a third diffusion region positioned along a portion of a second side of the third gate conductive structure, wherein the second gate conductive structure and the second diffusion region and the third diffusion region together form a second transistor; a first interconnect conductive structure defined in an interconnect level of the semiconductor device, the interconnect level of the semiconductor device positioned above the gate level of the semiconductor device, the first interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the first interconnect conductive structure separated from the lengthwise centerline of the first gate conductive structure by one-half of the first distance as measured in the second direction, the first interconnect conductive structure having a width measured in the second direction that is at least twice a width of the first gate conductive structure as measured in the second direction; a second interconnect conductive structure defined in the interconnect level of the semiconductor device, the second interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the second interconnect conductive structure separated from the lengthwise centerline of the first gate conductive structure by one-half of the first distance as measured in the second direction, the lengthwise centerline of the second interconnect conductive structure separated from the lengthwise centerline of the third gate conductive structure by one-half of the first distance as measured in the second direction, the second interconnect conductive structure having a width measured in the second direction that is at least twice the width of the first gate conductive structure as measured in the second direction; and a third interconnect conductive structure defined in the interconnect level of the semiconductor device, the third interconnect conductive structure having a linear-shape and a lengthwise centerline oriented in the first direction, the lengthwise centerline of the third interconnect conductive structure separated from the lengthwise centerline of the second gate conductive structure by one-half of the first distance as measured in the second direction, the third interconnect conductive structure having a width measured in the second direction that is at least twice the width of the first gate conductive structure as measured in the second direction.