HIGH SPEED CONTROLLABLE LOAD

摘要

A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test.

主权项

1. A method of testing an arc fault circuit interrupter (AFCI) comprising:
storing a waveform representative of an arc fault; coupling the AFCI and a controllable load in series with a power source; retrieving the stored waveform; sensing a current through the controllable load and the AFCI; adjusting a resistance in the controllable load based on the sensed current such that the current through the controllable load and the AFCI replicates the stored waveform at the AFCI.